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ADC4320/ADC4322/ ADC4325
Very High Speed 16-Bit, Sampling A/D Converters
in a Space-Saving 46-Pin Hybrid Package
Introduction
The ADC4320, ADC4322, and ADC4325 are complete 16-bit, 1 MHz, 2 MHz, and 500 kHz A/D converter subsystems with a built-in sample-andhold amplifier in a space-saving 46-pin hybrid package. They offer pinprogrammable input voltage ranges of 2.5V, 5V, 10V and 0 to +10V, and have been designed for use in applications, such as ATE, digital oscilloscopes, medical imaging, radar, sonar, and analytical instrumentation, requiring high speed and high resolution front ends. The ADC4322 is capable of digitizing a 1 MHz signal at a 2 MHz sampling rate with a guarantee of no missing codes from 0C to +70C, or in an extended temperature range version, from -25C to +85C. Equally impressive in frequency domain applications, the ADC4325 features 91 dB minimum signal-to-noise ratio with input signals from DC to 100 kHz. The ADC432X Series utilizes the latest semiconductor technologies to produce a cost-effective, high performance part in a 46-pin hybrid package. They are designed around a two-pass, sub-ranging architecture that integrates a low distortion sample-and-hold amplifier, precision voltage reference, ultra-stable 16-bit linear reference D/A converter, all necessary timing circuitry, and tri-state CMOS/TTL compatible output lines for ease of system integration. Superior performance and ease-of-use make the ADC432X Series the ideal solution for those applications requiring a sample-and-hold amplifier directly at the input to the A/D converter. Having the S/H amplifier integrated with the A/D converter benefits the system designer in two ways. First, the S/H has been designed specifically to complement the performance of the A/D converter; for example, the acquisition time, hold mode settling and droop rate have been optimized for the A/D converter, resulting in exceptional overall performance. Second, the designer achieves
Continued on page 5.
S/H IN 3 S/H IN 1 S/H IN 2 DNC -0.2 + + + - Residue Amp +1 10-Bit Flash ADC 9-Bit Data Trigger Transfer Lo Byte EN Gate Array Hi Byte EN O/U Flow B1 9-Bit DAC 16-Bit Linear 9-Bit Data B1-B16 + S/H ADC Clk S/H Control + + -1
Features
u 2 MHz, 1 MHz, and 500 kHz Conversion Rates u 16-Bit Resolution u 0.003% Maximum Integral Nonlinearity u No Missing Codes u Peak Distortion: -92 dB Max. (100 kHz Input) u Signal to Noise Ratio: 86 dB (ADC4322) Min. 89 dB (ADC4320) Min. 91 dB (ADC4325) Min. u Total Harmonic Distortion: (100 kHz Input) -86 dB (ADC4320) Max. -90 dB (ADC4325) Max. u TTL/CMOS Compatibility u Low Noise u Electromagnetic/Electrostatic Shielding
Applications
u u u u u u u u u Digital Signal Processing Sampling Oscilloscopes Automatic Test Equipment High-Resolution Imaging Analytical Instrumentation Medical Instrumentation CCD Detectors IR Imaging Sonar/Radar
Pass1/Pass2 -6.4 -4 MUX Amp
EXT OFF ADJ
+REF OUT -REF OUT Ext Gain Adj Reference
Timing Circuit
Figure 1. Functional Block Diagram.
ADC4320/ADC4322/ ADC4325
Specifications1
SPECIFICATION ANALOG INPUT Input Voltage Range Bipolar Unipolar Max. Input Without Damage Input Impedance 2.5V 5.0V, 0-10V 10V Offset/Gain Adj. Sensitivity DIGITAL INPUTS Compatibility Logic "0" Logic "1" Trigger Loading TriggerPulse Width High Byte Enable Low Byte Enable DIGITAL OUTPUTS Fan-Out Logic "0" Logic "1" Output Coding Transfer Pulse Over/Under Flow DYNAMIC CHARACTERISTICS2 Maximum Throughput Rate A/D Conversion Time S/H Acquisition Time S/H Aperture Delay S/H Aperture Jitter S/H Feedthrough3 Full Power Bandwidth Small Signal Bandwidth Signal to Noise Ratio4 100 kHz Input @ 0 dB 495 kHz Input @ -10 dB 980 kHz Input @ -10 dB Peak Distortion4 100 kHz Input @ 0 dB 495 kHz Input @ -10 dB 980 kHz Input @ -10 dB Total Harmonic Distortion4 100 kHz Input @ 0 dB 495 kHz Input @ -10 dB 980 kHz Input @ -10 dB THD + Noise5 100 kHz Input @ 0 dB 495 kHz Input @ -10 dB 980 kHz Input @ -10 dB 500 kHz 1.1 s Typ. 900 ns Typ. 15 ns Max. 5 ps RMS Max. -90 dB Max.; -96 dB Typ. 2.6 MHz Min. 2.6 MHz Min. 91 dB Min.;93 dB Typ. - - -92 dB Max.; -97 dB Typ. - - -90 dB Max.; -95 dB Typ. - - 88 dB Min.; 91 dB Typ. - - 1.0 MHz 620 ns Typ. 380 ns Typ. 15 ns Max. 5 ps RMS Max. -90 dB Max.; -96 dB Typ. 3 MHz Min. 6 MHz Min. 89 dB Min.; 92 dB Typ. 79 dB Min.; 82 dB Typ. - -92 dB Max.; -97 dB Typ. -84 dB Max.; -95 dB Typ. - -86 dB Max.; -94 dB Typ. -79 dB Max.; -86 dB Typ. - 84 dB Min.; 91 dB Typ. 76 dB Min.; 81 dB Typ. - 2.0 MHz 300 ns Typ. 200 ns Typ. 15 ns Max. 5 ps RMS Max. -90 dB Max.; -96 dB Typ. 6 MHz Min. 8 MHz Min. 86 dB Min.; 88 dB Typ. 76 dB Min.; 78 dB Typ. 75 dB Min.; 78 dB Typ. -92 dB Max.; 97 dB Typ. -84 dB Max.; -95 dB Typ. -81 dB Max.; -88 dB Typ. -86 dB Max. -94 dB Typ. -80 dB Max.; -88 dB Typ. -80 dB Max.; -85 dB Typ. 83 dB Min.; 87 dB Typ. 75 dB Min.; 77 dB Typ. 74 dB Min.; 77dB Typ. 1 TTL Load +0.4V +2.4V Binary, Offset Binary, Two's Complement Data valid on positive edge Valid = logic "0" (occurs only when FS have been exc'd.) 1 TTL Load +0.4V +2.4V Binary, Offset Binary, Two's Complement Data valid on positive edge Valid = logic "0" (occurs only when FS have been exc'd) 1 TTL Load +0.4V +2.4V Binary, Offset Binary, Two's Complement Data valid on positive edge Valid = logic "0" (occurs only when FS have been exc'd) TTL, HCT, and ACT +0.8V Max. +2.0V Min. Negative Edge Triggered 2 HCT Loads 100 ns Min. Active Low, B1-B8, B1 Active Low, B9-B16 TTL, HCT, and ACT +0.8V Max. +2.0V Min. Negative Edge Triggered 2 HCT Loads 100 ns Min. Active Low, B1-B8, B1 Active Low, B9-B16 TTL, HCT, and ACT +0.8V Max. +2.0V Min. Negative Edge Triggered 2 HCT Loads 50 ns Min. Active Low, B1-B8, B1 Active Low, B9-B16 2.5V, 5V, 10V 0 to +10V 15.5V 750 1.5 K 3 k 300 ppm FSR/V 2.5V, 5V, 10V 0 to +10V 15.5V 750 1.5 K 3 k 300 ppm FSR/V 2.5V, 5V, 10V 0 to +10V 15.5V 750 1.5 K 3 k 300 ppm FSR/V ADC4325 ADC4320 ADC4322
SPECIFICATION (CONT.) Step Response6 INTERNAL REFERENCE9 Voltage Stability Available Current7 Resolution Integral Nonlinearity Differential Nonlinearity Monotonicity No Missing Codes Offset Error Gain Error Noise8 10V p-p FSR 5V p-p FSR
ADC4325 800 ns Max. to 1 LSB +5V, 0.5% Max. 15 ppm/C Max. 1.0 mA Max. 16 bits 0.75 LSB; 0.5 LSB Typ. Guaranteed Guaranteed over the Specified Temperature Range 0.1% FSR Max. (Adj. to Zero) 0.1% FSR Max. (Adj. to Zero)
ADC4320 500 ns Max. to 1 LSB +5V, 0.5% Max. 15 ppm/C Max. 1.0 mA Max. 16 bits 0.75 LSB; 0.5 LSB Typ. Guaranteed Guaranteed over the Specified Temperature Range 0.1% FSR Max. (Adj. to Zero) 0.1% FSR Max. (Adj. to Zero)
ADC4322 250 ns Max. to 2 LSBs +5V, 0.5% Max. 15 ppm/C Max. 1.0 mA Max. 16 bits 0.75 LSB Max.; 0.5 LSB Typ. Guaranteed Guaranteed over the Specified Temperature Range 0.1% FSR Max. (Adj. to Zero) 0.1% FSR Max. (Adj. to Zero)
TRANSFER CHARACTERISTICS 0.003% FSR Max.; 0.001% Typ. 0.003% FSR Max.; 0.001% Typ. 0.003% FSR Max.; 0.001% Typ
55 V RMS Typ.; 70 V RMS Max. 65 V RMS Typ.; 80 V RMS Max. 90 V RMS Typ.; 110 V Max. 45 V RMS Typ.; 55 V RMS Max. 50 V RMS Typ.; 60 V RMS Max. 65 V RMS Typ., 80 V Max. 1 PPM/C MAX 15 ppm/C Max. 15 ppm/C Max. 5 Min. Max. 10 ppm/% Max. 14.55V Min., 15.45V Max. +4.75V Min., +5.25V Max. 63 mA Typ. 54 mA Typ. 67 mA Typ. 2.1W Typ. .1 PPM/C MAX. 15 ppm/C Max. 15 ppm/C Max. 5 Min. Max. 10 ppm/% Max. 14.55V Min., 15.45V Max. +4.75V Min., +5.25V Max. 71 mA Typ. 61 mA Typ. 67 mA Typ. 2.3W Typ.
STABILITY Differential Nonlinearity TC 1 PPM/C MAX. Offset TC Gain TC Warm-Up Time 15 ppm/C Max. 15 ppm/C Max. 5 Min. Max.
Supply Rejection per % change in any supply Offset & Gain 10 ppm/% Max. POWER REQUIREMENTS 15V Supplies9 +5V Supplies +15V Current Drain -15V Current Drain +5V Current Drain 14.55V Min., 15.45V Max. +4.75V Min., +5.25V Max. 63 mA Typ. 54 mA Typ. 67 mA Typ.
Total Power Consumption 2.1W Typ. ENVIRONMENTAL & MECHANICAL Specified Temp. Range10 A Version B Version Storage Temp. Range Dimensions Case Potential 0C to +70C -25C to +85C -25C to 125C 1.58" x 2.38" x 0.225" (40.13 mm x 60.45 mm x 5.7 mm) Ground
0C to +70C -25C to +85C -25C to 125C 1.58" x 2.38" x 0.225" (40.13 mm x 60.45 mm x 5.7 mm) Ground
0C to +70C -25C to +85C -25C to 125C 1.58" x 2.38" x 0.225" (40.13 mm x 60.45 mm x 5.7 mm) Ground
NOTES: 1. All specifications guaranteed at 25C unless otherwise noted and supplies at 15V and +5V. 2. All dynamic characteristics measured on the 5V input range except the 980 kHz distortion test are performed at the 2.5V input range. 3. Measured with a full scale step input. 4. See performance testing. 5. THD + noise represents the ratio of the RMS value of the signal to the total RMS noise below the Nyquist plus the total harmonic distortion up to the 100th harmonic with an analysis bandwidth of DC to the converters' Nyquist frequency.
6. Step response represents the time required to achieve the specified accuracies after an input full scale step change. 7. Reference Load to remain stable. 8. Includes noise from S/H and A/D converter. 9. Both 15V analog supply voltages and both reference voltages, Pins 2, 3, 16, and 17 must be by-passed with low ESR tantalum capacitors (see Figure 20). 10. The specified temperature range is guaranteed for the case temperature. Specifications subject to change without notice.
TYPICAL PERFORMANCE CHARACTERISTICS
Fig. 2. ADC4325 Dynamic Characteristics at 100 kHz and 0 dB
Fig. 6. ADC4325 Dynamic Characteristics at 195 kHz and -6 dB (5V Range)
Fig. 3. ADC4320 Dynamic Characteristics at 100 kHz and 0 dB
Fig. 7. ADC4320 Dynamic Characteristics at 495 kHz and -6 dB Range.
Fig. 4. ADC4322 Dynamic Characteristics at 100 kHz and 0 dB
Fig. 8. ADC4322 Dynamic Characteristics at 980 kHz and -6 dB (2.5V Range)
Fig. 5. ADC4322 Dynamic Characteristics at 495 kHz and 0 dB (2.5V Range)
Fig. 9. ADC4320 Intermodulation Distortion at 100 kHz, 125 kHz and -6 dB
SPECIFICATIONS
PIN # RANGE 0V to +10V 5V 2.5V 10V
4 S/H IN 1 Input Input Input Input
5 S/H IN2 Input Input Input SIG RTN
6 S/H IN 3 -5V Ref SIG RTN Input SIG RTN
Figure 13. Input Scaling Connections.
Continued from page 1.
Figure 10. ADC4322 SFDR vs Input Level @ 195 kHz 2.5V Range
true 16-bit performance, avoiding degradation due to ground loops, signal coupling, jitter and digital noise introduced when separate S/H and A/D converters are interconnected. Furthermore, the accuracy, speed, and quality of the ADC432X Series are fully ensured by thorough, computer-controlled factory tests of each unit.
INTERFACING Input Scaling
The converters can be configured for four input voltage ranges: 0 to +10V; 2.5V; 5V; and 10V. The analog input range should be scaled as close as possible to the maximum input to utilize the full dynamic range of the converter. Figure 13 describes the input connections.
Coding and Trim Procedure
Figure 11. ADC4322 SFDR vs Input Level @ 495 kHz 2.5V Range
Figure 15 shows the output coding and trim calibration voltages of the converter. For two's complement operation, simply use the available B1 (MSB) instead of B1 (MSB). Refer to Figure 14 for use of external offset and gain trim potentiometers. Voltage DACs with a 5V output can be utilized easily when digital control is required. The input sensitivity of the external offset and gain control pins is 300 ppm FSR/V. If Offset and Gain adjusts are not used, connect them to Pin 14, Analog Returns. To trim the offset of the converter, apply the offset voltage shown in Figure 15 for the appropriate voltage range. Adjust the offset trim potentiometer such that the 15 MSBs are "0" and the LSB alternates equally between "0" and "1" for the unipolar ranges or all 16 bits are in transition for the bipolar ranges.
Figure 12. ADC4322 SFDR vs Input Level @ 980 kHz 2.5V Range
To trim the gain of the converter, apply the range (+FS) voltage shown in Figure 15 for the appropriate range. Adjust the gain trim potentiometer such that the 15 MSBs are "1" and the LSB alternates equally between "0" and "1".
Gain Adj. +5V REF
R1 R1 = 50K R2 = 50K R2 C1 C2 C1 = 0.1 F C2 = 0.1 F
Off Adj. Gnd. -5V REF
Note: If not used, connect Pins 13, 14, and 15
Figure 14. Offset and Gain Adjustment Circuit.
UNIPOLAR BINARY 0V TO +10V
MSB LSB +FS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * = +9.99977V 1/2 FS 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = +5.00000V Offset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * = +0.00000V OFFSET BINARY +FS Offset -FS 2.5V Input 5V Input
MSB LSB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * = +2.49989V +4.99977V * * * * * * * * * * * * * * = -0.00004V -0.00008V 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * = -2.49996V -4.99992V 2.5V Input 5V Input
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
ANA RTN +15V -15V S/H IN 1 S/H IN 2 S/H IN 3 SIG RTN DNC* ANA RTN +15V -15V DNC EXT OFFSET ADJ ANA RTN EXT GAIN ADJ +REF OUT -REF OUT ANA RTN TRIGGER DIG RTN DIG RTN HI BYTE EN LO BYTE EN
PIN# 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24
+5V DIG RTN O/U FLOW BIT 1N BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 BIT 13 BIT 14 BIT 15 BIT 16 TRANSFER +5V DIG RTN
2'S COMPLEMENT +FS Offset -FS
* DNC- Do Not Connect
MSB LSB 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * = +2.49989V +4.99977V * * * * * * * * * * * * * * = -0.00004V -0.00008V 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * = -2.49996V -4.99992V
Figure 18. Pin Assignment.
To check the trim procedure, apply 1/2 full scale voltage for a unipolar range or -full scale voltage for the bipolar ranges and check that the digital code is 1 LSB of the stated code.
* denotes a 0/1 or 1/0 transition
Figure 15. Coding and Trim Calibration Table.
N N+1
PRINCIPLE OF OPERATION
The ADC432X Series converters are 16-bit sampling A/D converters with throughput rates of up to 2 MHz. These converters are available in three externally configured full scale ranges of 5V p-p, 10V p-p and 20V p-p. Options are externally or user-programmable for bipolar and unipolar inputs of 2.5V, 5V, 10V and 0 to +10V. Two's complement format can be obtained by utilizing B1 instead of B1.
Trigger S/H Cont (Internal) A/D Clock (Internal) Transfer Data N-1 Data N Data
25 ns Min.
Hold
Sample
Time (ns)
0
ADC4325 ADC4320 ADC4322
1.1 s 1.3 s 620ns 750ns 300 ns 400 ns
2.0 s 1.0s 500 ns
Figure 16. Timing Diagram.
S/H In 1 S/H In 2 S/H In 3 S/H Amp A= -1 or -2 10V p-p - + A= -0.2 S/H In 1 S/H In 2 S/H In 3 S/H Amp A= -1 or -2 10V p-p 1st Pass To DAC (2nd Pass) 9 2V p-p 10-Bit ADC 9 Logic
2.4" (60.96 mm) 0.100" (2.54 mm) Typ. (on center)
46
24
DAC In From Logic 9 16-Bit Linear DAC 0.5V p-p - + A= -6.4 A= -4 2nd Pass - + 10-Bit ADC 9 16 Logic O/U Flow B1-B16 B1 Transfer
1.3" 33.02 mm (on center)
Top View
1.300 (33 mm) 1.6 (40.64 mm)
w
23
0.225 Min. 0.225 Max.
0.018 (0.45 mm) Dia. Typ.
Figure 19. Operating Principle.
Figure 17. ADC432X Series Mechanical Diagram.
To understand the operating principles of the A/D converters, refer to the timing diagram of Figure 16 and the simplified block diagram of Figure 19. The simplified block diagram illustrates the two successive passes in the sub-ranging scheme of the converters. The A/D converter is factory-trimmed and optimized to operate with a 10V p-p input voltage range. Scaling resistors at the S/H inputs configure the three input ranges and provide a S/H output voltage to the A/D converter of 10V p-p. The first pass starts with a high-to-low transition of the trigger pulse. This signal places the S/H into the Hold mode and starts the timing logic. The path of the 10V p-p input signal during the first pass is through a 5:1 attenuator circuit to the 10-bit ADC with an input range of 2V p-p. At 35 ns, the ADC converts the signal and the 9 bits are latched both into the logic as the MSBs and into the 16-bit accurate DAC for the second pass. The second pass subtracts the S/H output and the 9bit, 16-bit accurate DAC output with the result equal to the 9-bit quantization error of the DAC, or 19.5 mV p-p. The "error" voltage is then amplified by a gain of 25.6 and is now 0.5V p-p or 1/4 the full scale range of the ADC, allowing a 2-bit overlap safety margin. When the DAC and the "error" amplifier have had sufficient time to settle to 16-bit accuracy, the amplified "error" voltage is then digitized by the ADC with the 9-bit second pass result latched into the logic. At this time the S/H returns to the sample mode to begin acquiring the next sample. The 1/4 full scale range in the second pass produces a 2-bit overlap of the two passes. This provides an output word that is accurate and linear to 16 bits. This method corrects for any gain and linearity errors in the amplifying circuitry, as well as the 10-bit flash A/D converter. Without the use of this overlapping correction scheme, it would be necessary that all the components in the converters be accurate to the 16-bit level. While such a design might be possible to realize on a laboratory benchtop, it would be clearly impractical to achieve on a production basis. The key to the conversion technique used in the converters is the 16-bit ac-
curate and 16-bit linear D/A converter which serves as the reference element for the conversion's second pass. The use of proprietary sub-ranging architecture in the converters results in a sampling A/D converter that offers unprecedented speed and transfer characteristics at the 16-bit level. The converter has a 3-state output structure. Users can enable the eight MSBs and B1 with HIBYTEN and the eight LSBs with LOBYTEN (both are active low). This feature makes it possible to transfer data from the converter to an 8-bit microprocessor bus. However, to prevent the coupling of high frequency noise from the microprocessor bus into the A/D converter, the output data must be buffered.
Layout Considerations
Because of the high resolution of the A/D converters, it is necessary to pay careful attention to the printed-circuit layout for the device. It is, for example, important to keep analog and digital grounds separate at the power supplies. Digital grounds are often noisy or "glitchy," and these glitches can have adverse effects on the performance of the converters if they are introduced to the analog portions of the A/D converter's circuitry. At 16-bit resolution, the size of the voltage step between one code transition and the succeeding one for a 5V full scale range is only 76 V. It is evident that any noise in the analog ground return can result in erroneous or missing codes. It is important in the design of the PC board to configure a low-impedance groundplane return on the printed-circuit board. It is only at this point where the analog and digital power returns should be made common. The Analogic ADC4322 EB-1 evaluation board has been designed and laid out for optimum performance with the converter series. The board layout and schematic are shown in figures 20-22 as examples of decoupling and layout techniques.
+5V P4 DGND P5 +15V P1 AGND P2 -15V P3 L2 C3 + TANT 6.8 F 20V C5 + TANT 6.8 F 20V C9 75pF/POLYS R6 +15V BNC1 1 Sig In1 2 E1 R5 2.5K.1% E2 -15V R8 20 C12 75pF/POLYS R10 +15V BNC2 1 Sig In2 2 E3 R9 2.5K.1% E4 -15V BNC3 1 R2A Trigger Position for 1/2 W Res 2 R2B +5V C7 + TANT 10 F 16V VCC C8 .1 F Y1 GND 2 MHz Out OSC 12 14 16 2 4 6 J1 J1 J1 J1 J1 J1 +5V R12 20 2.5K.1% R11 6
V+ TR2 TR1
L1 C1 + TANT 10 F 16V 25 H + C1 TANT 10 F 16V E18 E17 C4 TANT 6.8 F 20V + C6 TANT 6.8 F 20V E5 E7 E8 E9 E16 2 3 4 5 6 7 8 9 1 19
A A A A A A A A G1 G2
18
J1
OUFLOW
25 H +
L3 25 H
AD Converter
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 C21 ANARTN1 +15V1 -15V1 S/HIN1 S/HIN2 S/HIN3 SIGATN DNC ANARTN2 +15V2 -15V2 DNC OFFADJ ANARTN3 GAINADJ +REFOUT -REFOUT ANARTN4 TRIGGER DIGRTN DIGRTN HIBYTE/EN LOBYTE/EN +5V2 DIGATN2 O/UFLOW BIT1 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT8 BIT9 BIT10 BIT11 BIT12 BIT13 BIT14 BIT15 BIT16 TRANSFER +5V1 DIGRTN1 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24
U1 Y U1 Y U1 Y U1 Y U1 Y U1 Y U1 Y U1 Y VCC U1 GND
18 17 16 15 14 13 12 11 20 10
E6 C10 TANT 6.8 F 20V 6
20 22 24 26 28 30 32 34 +5V C15 1F 3
J1 J1 J1 J1 J1 J1 J1 J1
D15 (MSB) D14 D13 D12 D11 D10 D09 D08
J1
HIBYTEN
2.5K.1% R7 6
V+ TR2 TR1
20 2 3
78 9
- +
+
V-
U4 AD845
4
C11 TANT 6.8 F 20V +
E10 E11 E12 E13 TANT 6.8 F 20V C19 R13 50KTADJ +
2 3 4 5 6 7 8 9 1 19
A A A A A A A A G1 G2
U2 Y U2 Y U2 Y U2 Y U2 Y U2 Y U2 Y U2 Y VCC U2 GND
18 17 16 15 14 13 12 11 20 10
74LS541
36 38 40 42 44 46 48 50 +5V C16 1F 5
J1 J1 J1 J1 J1 J1 J1 J1
D07 D06 D05 D04 D03 D02 D01 D00 (LSB)
J1
LOBYTEN
20 2 3
78 9
- +
+
C13 TANT 6.8 F 20V 6
.1F R13 50KTADJ Range C22 C20 + .1 F TANT 6.8 F 20V 1 E15 U3 2 HCT00 1 J1 7 J1 9 J1 11 J1 13 J1 15 J1 17 J1 19 J1 21 J1 23 J1 47 J1 49 J1 2.5V 5V 10V 0/+10V Configuration J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 J1 Sig In1 Direct Sig In1 AD845 2 Tone 2.5V 2 Tone 5V Internal Trig External Trig Normal Data 2's Comp Data Jumpers E7, E10 E7, E13 E9, E13 E7, E12 Jumpers E2, E4, E5 E1, E4, E6 E1, E3, E6, E7, E11 E1, E3, E6, E8, E13 E15 E14 E16 E17 E19 E20 9 10 HCT00 4 5 U3 HCT00 8 6
E21 E22 12 13 +5V U3 HCT00 11 R3 8 J1 READY 10
V-
U5 AD845
J1
DATASTRB
4
C14 TANT 6.8 F 20V +
E14
220 R4 330
14 HCT00 VCC U3 GND
C18 C17 + TANT 1F 10 F 16V 7
25 27 29 31 33 35 37 39 41 43 45
Figure 20. ADC4322-EB1 Block Diagram
Figure 21. Primary Side
Figure 22. Secondary Side
Ordering Guide
Specified Temperature Range: 0C to +70C Model Sampling Rate ADC4325A 500 kHz ADC4320A 1 MHz ADC4322A 2 MHz Specified Temperature Range: -25C to +85C ADC4325B 500 kHz ADC4320B 1 MHz ADC4322B 2 MHz Evaluation Board ADC4322 EB-1

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